The relentless pursuit of miniaturized, high speed semiconductor devices continues to challenge the limitations of conventional semiconductor materials and fabrication techniques. Conventional semiconductor devices typically comprise a plurality of active devices in or on a common semiconductor substrate, e.g., CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency. Current technology utilizes crystalline semiconductor wafers as substrates, such as a lightly p-doped epitaxial (“epi”) layer of silicon (Si) grown on a heavily-doped, crystalline Si Substrate. The low resistance of the heavily-doped substrate is necessary for minimizing susceptibility to latch-up, whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p-type and n-type wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance.
The use of the very thin epi layers, i.e., several μm thick, is made possible by utilizing shallow trench isolation (“STI”), which advantageously minimizes up-diffusion of p-type dopant(s) from the more heavily-doped substrate into the lightly-doped epi layer. In addition, STI allows for closer spacing of adjacent active areas by avoiding the “bird's beak” formed at the edge of each LOCOS isolation structure. STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations.
Substrates based on “strained silicon” have attracted interest as a semiconductor material which provides increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. A very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition of silicon-germanium (Si—Ge) buffer layer several microns thick, which Si—Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. The Si—Ge buffer layer typically contains 12 to 25 at. % Ge. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Si—Ge buffer layer, to align with the greater lattice constant (spacing) of Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Si—Ge) comprised of atoms which are spaced further apart, they “stretch” to align with the underlying Si and Ge atoms, thereby “stretching” or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
The mobility of electrons is faster than the mobility of holes in conventional bulk silicon substrates. Accordingly, in conventional CMOS transistors, the drive current of the PMOS transistor is less than the drive current of the NMOS transistor creating an imbalance. This imbalance is exacerbated in CMOS transistors fabricated on or within a tensilely stressed active device area formed in a strained lattice semiconductor substrate, e.g., strained Si on Si—Ge, because the increase in electron mobility is greater than the increase in hole mobility.
Conventional practices used to fabricate various types of semiconductor devices comprise depositing a dielectric layer, such as a interlayer dielectric, as by subatmospheric chemical vapor deposition (SACVD), e.g., silicon oxide derived from tetraethyl orthosilicate (TEOS). However, due to a reverse loading effect, the oxide film is deposited in isolated areas at a thickness less than in dense areas. Thus, there is an undesirable thickness dependence of the deposited dielectric layer upon the surface patterns during gap filling. As micro-miniaturization proceeds, there is an attendant need to increase the drive current of transistors, including transistors formed on strained Si/Si—Ge substrates, by enhancing carrier mobility.
Accordingly, there exists a need for efficient methodology enabling the fabrication of semiconductor devices with enhanced drive currents by increasing channel carrier mobility, and for efficient methodology enabling the deposition of dielectric layers with no or significantly reduced deposition surface pattern sensitivity during gap filling.